1. Field of the Invention
The present invention relates to the field of gallium nitride (GaN) devices and, more particularly, to the fabrication of GaN integrated circuits using one or more polysilicon layers to fabricate active and passive silicon devices.
2. Description of the Related Art
Gallium nitride (GaN) semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most gallium nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
FIGS. 1A-1H illustrate a conventional manufacturing process for fabricating an enhancement mode (normally off) GaN transistor. As shown in FIG. 1A, the exemplary device is formed by first depositing a number of layers on a substrate 10, formed from silicon (Si), silicon carbide (SiC) or the like. In particular, an aluminum nitride (AlN) seed layer 11 is deposited on the substrate 10, an aluminum gallium nitride (AlGaN) layer 12 is formed on the seed layer 11, and one or more gallium nitride (GaN) layers 13 with different kinds of doping are formed on the AlGaN layer 12. Furthermore, an aluminum gallium nitride (AlGaN) barrier layer 14 is formed on the GaN layer 13, a pGaN layer 15 is formed on the barrier layer 14, and a gate metal 16 is formed on the pGaN layer 15. As further shown in FIG. 1A, a photoresist 17 is deposited as a protecting layer on the gate metal 16 to define the gate pattern using the photoresist.
Next, as shown in FIG. 1B, the gate metal 16 and the pGaN material (i.e., crystal) 15 are etched with the photoresist 17 serving as the protecting layer. As then shown in FIGS. 1C and 1D, an insulating layer or film 18 is deposited and contact openings 19A and 19B are formed for the source and drain contacts. Next, a first aluminum metal is deposited to define the metal pattern. As shown in FIG. 1E, the metal layer can form the source metal 20A, the drain metal 20B, and optionally a field plate 20C. An interlayer dielectric is then deposited as shown in FIG. 1F. In this example, the insulator 18 is the same material as that deposited in FIG. 1C.
Once the interlayer dielectric 18 is deposited, vias 22A and 22B can be cut between metal layers as shown in FIG. 1G The vias can be filled with tungsten to form a plug and a second aluminum metal layer can be deposited to form metals 21A and 21B. This step can be performed again as shown in FIG. 1H with additional vias cut 24A and 24B and additional metals 23A and 23B formed. A passivation layer 25 can then be deposited over the third aluminum metals 23A and 23B. FIG. 2 shows a scanning electron micrograph of the GaN structure formed by the process of FIGS. 1A-1H.
One limitation of the process described above in FIGS. 1A-1H is that the device fabricated is a single enhancement mode device on a chip. A second limitation is that a GaN HEMT device, as mentioned above, uses a highly conductive electron gas (2DEG), and is therefore an n-channel transistor. However, it is difficult to make a p-channel transistor due to very poor hole mobility in gallium nitride. Moreover, it is also difficult to fabricate other types of silicon devices in gallium nitride.
Accordingly, it would be desirable to have a process for forming GaN integrated circuits that include silicon active and inactive components that have otherwise been difficult to fabricate in gallium nitride.